There has recently been an increasing demand to conduct IC test in Si wafer unit. With the upsizing of Si wafers, it is currently demanded to conduct such test even on φ300 mm (12-inch) Si wafers. For the test of these wafers, a measurement jig needs to be formed with a connection terminal for contact with a pad of the wafer.
As the measurement jig is used repeatedly upon contact with wafers to be tested, it is required that a substrate of the measurement jig has high strength to withstand repeated measurements. From this point of view, a ceramic substrate is used as the substrate of the measurement jig. The ceramic substrate is generally manufactured by producing a sintered ceramic body through a predetermined sintering process and performing a polishing treatment to smoothen front and back surfaces of the sintered ceramic body and thereby adjust the sintered ceramic body to a given thickness.
By the above polishing treatment, however, microcracks occur in front and back surfaces of the ceramic substrate so that the front and back surfaces of the ceramic substrate have brittle layers containing these microcracks at surface portions thereof. This causes deterioration in the strength of the ceramic substrate and results in failure to exert the intrinsic high-strength characteristics of the ceramic substrate adequately.
In view of such a problem, for example, Patent Document 1 describes an attempt to modify and repair the brittle layers of the ceramic substrate by, after the polishing treatment, heat treating the ceramic substrate in a temperature range lower than a sintering temperature of the ceramic substrate. However, there is a case where the ceramic substrate shrinks again by the heat treatment and shows a large derivation from the target dimensions. Namely, the dimension accuracy of the ceramic substrate can be deteriorated by the heat treatment.
There is also a problem that, in the case of forming a wiring layer in the ceramic substrate, the wiring layer gets deformed by the heat treatment so that the ceramic substrate cannot be produced as designed.
On the other hand, for the production of the measurement jig, the wafer-test connection terminal is formed on one main surface of the ceramic substrate manufactured through the above process steps. With the repeated use of the measurement jig, the connection terminal is repeatedly brought into contact with the wafers to be tested. It is thus required that the connection terminal has high adhesion strength and high connection reliability to the ceramic substrate.
However, the brittle layer is present at the surface portion of the ceramic substrate immediately after the polishing treatment as mentioned above so that the connection terminal is joined to the ceramic substrate through the brittle layer. This brittle layer can be broken by e.g. a long-term stress load because of its brittleness. Not only the substantial joint strength of the connection terminal to the ceramic substrate but also the connection reliability between the connection terminal and the ceramic substrate are deteriorated in the occurrence of breakage of the brittle layer during the repeated use of the measurement jig.
There is further a problem that the connection terminal gets deformed by the heat treatment for modification and repair of the brittle layer.
By forming the connection terminal after the modification and repair of the brittle layer, it is possible to avoid the above problem but is not yet possible to attain sufficient joint strength between the ceramic substrate and the connection terminal.
Further, Patent Document 2 describes an attempt to perform lapping treatment on the ceramic substrate with free abrasive grains after the polishing treatment and thereby remove the brittle layer from the ceramic substrate. In this technique, it is possible to improve the strength of the ceramic substrate but is not possible to improve the joint strength between the ceramic substrate and the connection terminal.
There is also a problem in the technique of Patent Document 2 that, in the case of forming a wiring layer and a via conductor layer in the ceramic substrate, the wiring and via conductor layers protrude from the ceramic substrate due to a difference in polishing amount between the ceramic substrate and the wiring and via conductor layers. This can lead to improper formation of the connection terminal.
Furthermore, Patent Documents 3 and 4 disclose a technique for fixing the connection terminal (input/output pin) to the ceramic substrate by brazing. As the adhesion strength between the ceramic substrate and a conductor layer to which the input/output pin is connected is not sufficient, the layer structure of the conductor layer is studied in Patent Document 3 so as to relieve stress on the conductor layer. In Patent Document 4, the brazing of the connection terminal to a cover-coated conductor layer is studied in consideration of the adhesion strength between the ceramic substrate and the conductor layer.    Patent Document 1: Japanese Laid-Open Patent Publication No. 5-235551    Patent Document 2: Japanese Laid-Open Patent Publication No. 5-075264    Patent Document 3: Japanese Laid-Open Patent Publication No. 8-115999    Patent Document 4: Japanese Laid-Open Patent Publication No. 8-236938